Computing networks can include multiple network devices such as routers, switches, hubs, servers, desktop PCs, laptops, and workstations, among other peripheral devices, e.g., printers, facsimile devices, and scanners, networked together across a local area network (LAN) and/or wide area network (WAN). Internal to many of these network devices, there is often a processor responsible for processing packets used in the network device's global operation.
One approach to providing packets received at the external network ports to a processor on the network device, i.e., the processor responsible for processing the packets used in the network device's global operation, was to put the processor access in a central place such as in the switching fabric. This approach introduces complex port forwarding logic into an otherwise straightforward crossbar switching fabric and introduces two sets of code to keep in step with one another. Moreover, the approach is not available in a small network chip configuration which may not use a switching fabric chip.
Another approach to providing packets received at the external network ports to the processor responsible for processing those packets has been to provide a special management blade, e.g., processor and memory chip dedicated to handling the exchange of those packets. In this approach, the network device is hard coded so that all of this particular processor traffic goes through the management blade. A disadvantage to this approach is that, if the management blade fails or needs to be removed, the entire network device is down.
Another approach has been to provide simultaneous connections from each network chip to the particular processor for processing these packets. The disadvantage to this approach is cost. That is, the particular processor will have as many media access control-physical layer (MAC-PHY) ports as there are network chips on the network device which does not scale particularly well. Moreover, this approach becomes more cumbersome when the network device endeavors to provide redundancy among the processors responsible for processing the packets in the event a given processor is busy or down.